1. Field of the Invention
The present invention relates to inspection of connections between terminals in a semiconductor device having a semiconductor integrated circuit, particularly to inspection of connections of a plurality of power source terminals and grounding terminals.
2. Description of Prior Art
First, a package mounted with a chip on which a semiconductor integrated circuit (LSI) is formed is described. For example, in the case of a plastic package, connection between signal lines of the chip and leads is achieved by connecting a pad coupled to the signal line to a lead with a wire. By the way, a problem may occur in the course of sealing the chip in the package. The problem is separation of a wire from a pad, resulting from inappropriate connection of the wire to the pad. Then, after the chip is sealed in the package, an LSI including a separated wire malfunctions. Thus, such an LSI needs to be considered as a defective product. Therefore, after mounting and sealing the chip in the package, it is necessary to inspect whether or not pads and leads are connected accurately with wires by an inspection device.
The connection inspecting method for investigating whether or not wires connecting signal lines of an LSI are electrically connected between leads and pads is as follows: a predetermined voltage is supplied to the power source terminal and grounding terminal of an LSI to be inspected (hereinafter referred to as a test LSI), and a test voltage is supplied to the lead corresponding to the connection to be inspected.
FIG. 16 is a configuration of a test LSI and an inspection device thereof relating to a conventional method for inspecting connections of signal lines.
With reference to FIG. 16, a test LSI 4′ includes wires W1, W2 and W3, and the wire W1 is connected to a cathode of a surge protection diode DU, the wire W3 is connected to an anode of a surge protection diode DL, and the wire W2 is connected to the connection between an anode of the surge protection diode DU and a cathode of the surge protection diode DL, each through an internal line of the test LSI.
To inspect whether the wire W2 is connected or unconnected, voltages of 3.3 V and 0 V are supplied respectively to leads L1 and L3 of the test LSI 4′ connected to the wires W1 and W3, and then a voltage of −0.8 V that causes a forward current of the surge protection diode DL to flow is supplied to a lead L2 connected to the wire W2.
If the wire W2 is connected, a forward current Ia flows in the surge protection diode DL, and the forward current Ia is detected by a voltage generator 12. The voltage generator 12 includes a voltage source and an ammeter for measuring a current outputted from the voltage source.
On the other hand, if the wire W2 is unconnected, a forward voltage is not supplied to the surge protection diode DL, so that no current flows. When a forward current of the surge protection diode DL flows, it can be determined that the wire W2 is connected. When a forward current does not flow, it can be determined that the wire W2 is unconnected. However, the connection inspection is limited to the case when the wire W2 is connected to a signal line. For example, a signal line connected to an input terminal of a digital circuit 6′ or the like is inspected.
Conventionally, there has been no appropriate method for inspecting the connection states of power source lines and grounding lines. This reason is described below with reference to FIG. 17.
FIG. 17 is a configuration of a test LSI and an inspection device thereof relating to a conventional method for inspecting connections of power source lines.
As power source terminals and grounding terminals of the LSI, a plurality of terminals are arranged to assure the operation frequency and operation precision required for the circuits inside the chip or the amount of power source noise. Described herein is a LSI including three power source terminals. A description of grounding terminals is omitted because it is the same as the power source terminals.
In FIG. 17, a voltage is supplied from the outside to the inside of the LSI by three leads L4, L5 and L6, wires W4, W5 and W6, and pads PD4, PD5 and PD6, which are located inside the chip of the test LSI 4′. That is, power source lines A, B and C branched from an LSI power source line 10′ are connected to a printed board power source line 8′ with three leads L4, L5 and L6 through pads PD4, PD5 and PD6, and wires W4, W5 and W6, respectively. Furthermore, although omitted in the drawing for simplification, a grounding voltage GND is supplied from the outside of the test LSI 4′ to anodes of surge protection diodes D1, D2 and D3, which are connected respectively to the power source lines A, B and C of the test LSI 4′.
Now, assume that there is a deficiency in the connection of the wire W5, and the LSI power source line 10′ is disconnected from the printed board power source line 8′. In this case, if a conventional inspection method for signal lines is applied to the inspection of the power source lines, the following problem occurs.
First, a voltage is supplied to the printed board power source line 8′ by the voltage generator 12. The voltage supplied by the voltage generator 12 to the printed board power source line 8′ is −0.8 V. The voltage of −0.8 V is the voltage when a forward current of the surge protection diodes flows. The surge protection diodes D1, D2 and D3 are connected respectively to the power source lines A, B and C, and a voltage that causes a forward current to flow is supplied. Therefore, although the wire W5 is unconnected, because it is connected to the LSI power source line 10′ in common with the wires W4 and W6, a forward current flows in the surge protection diode D2. As a result, forward currents Ia, Ib and Ic flow in the surge protection diodes D1, D2 and D3.
These currents are detected by the voltage generator 12 as a current I=Ia+lb+Ic. The forward current I flows even if the wire W5 is unconnected. When the wires W4, W5 and W6 are connected, forward currents are generated in the surge protection diodes D1, D2 and D3. When the wires W4 and W6 are connected but the wire W5 is unconnected, forward currents also are generated in the surge protection diodes D1, D2 and D3. Thus, there is no change in the amount of flowing current between the cases in which the wire W5 is unconnected or connected. As a result, the connection state of the wire W5 cannot be detected.
In the above-described example, even though the wire W5 is unconnected, forward currents flow in respective surge protection diodes when the wires W4 and W6 are connected. This is because, in the outside and the inside of the test LSI 4′, a plurality of power source lines are connected in parallel between the printed board power source line 8′ corresponding to an external power source line and the LSI power source line 10′ corresponding to an internal power source line, which are each a single power source line. The power source line inside the chip is commonized to avoid an increase in chip cost resulting from increase in the area of the power source line when the power source line inside the chip is divided for each power source terminal.
Furthermore, the printed board power source line 8′ used for inspecting the test LSI 4′ is commonized for the following reason.
On the outside of the LSI, it is desired that the impedance of the power source lines existing between the voltage generator 12 and the leads L4, L5 and L6 of the test LSI 4′ is decreased. Particularly, it is necessary to decrease inductance. Thus, the printed board power source line 8′ is not divided to reduce the linewidth, but the power source line is commonized to design a large width.
For example, taking advantage of the characteristic of small inductance of terminals with a ceramic chip sized package (hereinafter referred to as C-CSP) or the like, the use of C-CSP to increase the operation frequency of a circuit also has been increased. Also, in the case of a circuit requiring low impedance of power source terminals, it is also necessary to reduce the parasitic impedance on the power source line of the printed board mounted with an LSI on application. Otherwise, even when a package of low impedance is used, if the parasitic impedance on the power source line of the printed board is greater than that impedance, the integrated impedance becomes high, so that the characteristic of the low impedance of the package cannot be utilized effectively.
Furthermore, the printed board for inspection also needs to have decreased power source impedance. If the parasitic impedance on the power source line of the printed board for inspection is not decreased, the same condition as the operation on application cannot be realized. Thus, inspection is not performed with high precision. That is, as the LSI is mounted in a smaller package, there is a greater necessity for designing with a decreased parasitic impedance on the power source of the printed board for inspection.
After all, LSIs in the future will have a greater number of power source terminals, and there will be a greater necessity for designing with an emphasis on the impedance contained in power source terminals, particularly inductance. When the number of power source terminals and the number of the grounding terminals of an LSI are designed with greater precision, it is necessary to inspect whether or not all power source terminals are connected. This is for the small design margin. Thus, not only is the necessity for inspecting the power source terminals in digital circuits, memory circuits, etc. inside the LSI important, but also the necessity for inspecting the power source terminals in an output circuit for transferring the calculation results of the LSI as signals to an external signal receiver is at least as important.
The necessity for inspecting the connection states of power source terminals and grounding terminals will increase more than ever. Because the operation frequency of an LSI inevitably will increase in the future, it is necessary to decrease the inductances of power source lines and grounding lines. It is necessary to realize an inspection condition close to the operation on application of the LSI. Inspection of the connections of power source terminals and grounding terminals will guarantee better quality of an LSI.
Furthermore, a shorter inspection time is more favorable. However, there has been no inspection method satisfying such requirements.